Jaya Keshava Chandra Kotha
PhD Candidate · Computer Engineering · UC Irvine
Projects
Featured Projects
Lightweight Feature-Fusion Architecture for Tabular Classification. Implements a Dual-Path Neural Network designed for tabular classification tasks where both absolute counts and ratio-based features are important. The architecture separates these two feature types into two experts and fuses them using unidirectional context transfer.
Python tool to analyze dataset quality, identifying missing values, distribution skew, and label inconsistencies prior to model training.
Advanced neural network architecture combining multiple expert pathways for improved classification performance on complex datasets.
A minimal demo that visualizes and explains neural network layer activations using a Cloudflare Worker (AI passthrough), a small frontend UI, and a tiny Python helper to generate sample activation JSON.
A lightweight Chrome/Edge browser extension that lets you quickly copy your most-used links (LinkedIn, GitHub, portfolio, email) from a simple popup. Perfect for speeding up job applications and form filling.
A privacy-focused, account-aware Chrome extension that adds a native-feeling nested folder hierarchy to the Gemini sidebar, with quick chat assignment and local-only storage.
A Streamlit-based interface for reading Japanese text with Duolingo-style Romaji ruby annotations, line-by-line translation, and interactive Kanji tooltips. Optimized for iPad/mobile browsers via local network hosting.
Performance signal explorer for hardware counter time-series data, combining a FastAPI backend with a Streamlit frontend for interactive analysis. Explore single signals, compare runs, and build derived ratios with attack-region labeling and Plotly visualizations.
Adaptive Runtime Detection of Microarchitectural Attacks
Lightweight runtime detection system using hardware performance counters and machine learning to identify microarchitectural attacks across Intel and ARM platforms with minimal overhead.
Cache Evaluation using Gem5
Analyzed cache configurations on x86 to study latency vs throughput trade-offs.
FPGA Design using Verilog
Implemented basic CPU components and multiplexers for digital logic optimization.
Other Projects
Additional projects from my GitHub activity.